// Protocol for AKO I2C bus master chip /***********************/ /*** Version history ***/ /***********************/ 1.5 (04feb2000): Cleaned up document and fixed some inconsistencies. 1.4 (02feb2000): Changed Cmd_Success identifier bit and added additional fields to Cmd_Success. Added bit to Status word to indicate when the AKOI2C controls the bus. 1.3 (01feb2000): Removed IACK line and command. Data port read now acknowledges INTs. Data port reads are invalid unless the AKOI2C generated an INT. A command must be sent to the AKOI2C to be able to read the status of the chip. 1.2 (29jan2000): Revised section on generation and acknowledgement of interrupts 1.1 (16dec1999): Updated Flush command to execute asynchronously. Added buffer for interrupt data and status. Added pinout for 16F877. Added IDLE and BUSF flags to Status word. 1.0 (15dec1999): Initial version. /********************/ /*** Introduction ***/ /********************/ This document describes the interface of the AKO I2C bus master chip using an 8-bit parallel data bus. Interfacing this chip to other systems, such as a PC parallel port, or uCsimm, is not described in this document. The AKO I2C bus master chip is interfaces parallel 8-bit data lines to an I2C bus. It is capable of simultaneously running as a slave, and as a master in a multi-master environment. It utilizes 7-bit I2C addressing, and supports a clock rate of 100kHz (standard mode), 400kHz (fast mode), or 1MHz. The AKO I2C bus master chip interfaces through an 8-bit data line. The protocol consists of command bytes, and data that goes along with the command. A byte is intrepreted as a command when the previous command has finished receiving its data bytes. To facilitate communications, the AKO I2C bus master chip contains an 80 byte FIFO command/data buffer. An 80 byte interrupt status buffer is also included to help prevent interrupt data from being lost due to slow servicing. The preliminary AKO I2C bus master chip will interface to a system via an 8-bit data bus, chip select, read select, write select, and interrupt line. Later derivatives will support interfacing the chip using RS-232C serial lines. /**********************************************/ /*** Description of parallel bus connection ***/ /**********************************************/ Description of lines on AKO I2C bus master chip: D0-D7: The 8-bit bidirectional data port. ~CS: Active low chip select. ~RD: Active low read select. Pull low to select reading from data port. ~WR: Active low write select. Pull low to select writing to data port. INT: Level triggered interrupt indicator. This pin is high when an unacknowledged interrupt is pending. Interrupts are acknowledged by strobing reading the data port (~CS and ~RD low). ~RESET: Active low chip reset. Pinout on PIC16F877: D0: RD0 (19) D1: RD1 (20) D2: RD2 (21) D3: RD3 (22) D4: RD4 (27) D5: RD5 (28) D6: RD6 (29) D7: RD7 (20) ~CS: RE2 (10) ~RD: RE0 (8) ~WR: RE1 (9) INT: RB1 (34) ~RESET: ~MCLR (1) VDD: (11) and (32) VSS: (12) and (31) When no reads or writes are occurring to the chip, ~CS, ~RD, and ~WR should be high. To write to the chip: 1) Put data to write on D0-D7 lines. 2) Pull ~CS low. 3) Pull ~WR low. 4) Wait 20ns (according to 16F877 spec) 5) Return ~WR to high. 6) Return ~CS to high. 7) Not sure, but the 16F877 spec indicates that the D0-D7 might need to stay the same for another 20ns. It's hard to tell. Probably not a problem though. To read from chip: 1) Pull ~CS low. 2) Pull ~RD low. 3) Wait 80ns (according to 16F877 spec) 4) Read data off of D0-D7 lines. 5) Return ~RD high. 6) Return ~CS high. NOTE: The chip will also function properly if ~RD or ~WR are lowered before ~CS. Also, it is possible to use a single WR/~RD or RD/~WR select line and obtain the complement line with a NOT gate. In this situation, the proper select is chosen, and then ~CS is lowered. ////////////////////////////////// // Notes on writing to the chip // ////////////////////////////////// Almost all commands are a single byte. When using a multi-byte command, such as Master_Xmit, care should be taken that no other data writes become interleaved into the Master_Xmit command stream. //////////////////////////////////// // Notes on reading from the chip // //////////////////////////////////// If an interrupt is not pending (INT is not asserted), then reading the chip produces an undefined byte. The chip may only be read when an INT has been asserted. Reading the chip acknowleges the interrupt and causes the INT line to be deasserted. ///////////////////////////// // Initialization sequence // ///////////////////////////// Hard reset: 1) Pull ~RESET pin low. 2) Pull ~RESET pin high. 3) Write Rate command to set SCL clocking rate. 4) Write Slave command to set devices slave address. 5) Write Configure command to set chip options (if any). Soft reset: 1) Write Flush command to clear data buffer and release bus. 2) If no interrupt received, goto step 1 (chip was in middle of multi-byte command). 3) Acknowledge interrupt. 4) Read status word. 5) If status word is not for flush command completion, goto step 1. The chip defaults to 100kHz I2C, no slave functionality, interrupts for all START's and STOP's, interupts occur for each byte read from bus, slave disabled. //////////////// // Interrupts // //////////////// Interrupts are generated for a variety of conditions on the bus. These include START and STOP detected, byte(s) read from bus, command completion, buffer overflows, etc. Interrupts can be detected by monitoring the INT line of the chip. When an interrupt occurs, data is ready to be read from the 8-bit data port. Reading the data port acknowledges the interrupt and causes INT to be deasserted. An interrupt will be issued for every byte to be read from the port, even if the chip is in the middle of a multi-byte data read. /*************************/ /*** Commands (writes) ***/ /*************************/ When a write overflows the bus master's command buffer, and interrupt is generated. Upon acknowleding the interrupt, a Status byte will be read read from the data port which indicates that the buffer is full, and that the last byte written did not get queued. Name: Flush Command: 0x00 Data: No data. Desc: The reset command causes the bus master chip to surrender control of the I2C bus, and to flush its internal command buffer. Flush executes asynchronously, as soon as it is received. Errors: None Name: Start Command: 0x02 Data: No data. Desc: The start command causes the bus master chip to issue a start condition on the I2C bus. If the bus is busy and the BUSW bit is set in the Configure word, the chip will block until the bus is free and the START condition may be asserted. Otherwise, the start command will fail with a bus busy error. After a successful Start condition, the AKOI2C is in control of the bus. Errors: Bus collision (arbitration lost), bus not free. Name: Stop Command: 0x03 Data: No data. Desc: The stop command causes the bus master to issue a stop condition on the I2C bus. The AKOI2C must have obtained control of the bus with a Start command for Stop to succeed. After the Stop command is issued, the AKOI2C is no longer in control of the I2C bus. Errors: Bus collision (arbitration lost), not in control of bus. Name: Rate Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 0 | 0 | 1 | x | x | Data: Included in command word. Desc: Sets the I2C clock rate in master mode, and the slew control used on the SCL pin in slave mode. Settings: 0x04 - Select 100kHz master, standard mode slew control. 0x05 - Select 400kHz master, fast mode slew control. 0x06 - Select 1MHz master, standard mode slew control. 0x07 - Reserved. Using the reserved setting on the current firmware revision an undefined effect. Errors: None Name: Status Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 0 | 1 | x | x | UTIL | Data: Included in command word. Desc: Requests that the current AKOI2C status be given to the CPU. The Status byte will be queued to be read by the CPU at the tail of data queue. Note that the Status byte the CPU will read will be the chip status when the INT for the status byte was generated, not when the chip received the Status command. Settings: UTIL (b0) - Requests that in addition to the status word, the 16-bit I2C utilization count for the past 0.10 be appended after the status word, when UTIL == 0. b1 - Currently undefined. Should be 0 for future compatibility. b2 - Currently undefined. Should be 0 for future compatibility. Errors: None Name: Master_Xmit Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 1 | x | x | x | x | Data: Lower nibble (b0-b3) indicate the number of data words following this command word. The data to be transmitted follows this command word. Desc: Starts a burst transfer of data to be transmitted in master transmitter mode by the bus master chip. The data follows the command byte. The number of data bytes following is indicated by ((command & 0x0f) + 1). The data bytes follow immediatly after the command word. To prevent synchronization problems due to interleaving data from a Master_Xmit command and commands from an ISR, the interrupt is disabled until all data for the Master_Xmit command has been received. For this reason, the data should be written as quickly as possible to get the interrupts re-enabled. The AKOI2C must have gained control of the bus with a Start command for Master_Xmit to succeed. If Master_Xmit fails with an arbitration lost error, the AKOI2C is no longer in control of the I2C bus. Errors: Arbitration lost, not in control of bus, slave did not ACK Name: Master_Recv Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 1 | ACK | x | x | x | x | Data: Included in command word. Desc: Indicates that the bus master should read a series of words from the bus in master receiver mode. Bits b0-b3 indicate the number of bytes to be read. The ACK bit (b4), indicates if the last byte of the stream should be ~ACK'd. If ACK is asserted, the ~ACK will be sent on the last byte. If ACK is not asserted, then no ~ACK will be sent on the last byte, indicating the last byte of the transfer. The AKOI2C must have gained control of the bus with a Start command for Master_Recv to succeed. Errors: Not in control of bus Name: Configure Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 1 | u | u | SLACT| SSINT| MARD | SLRD | Data: Included in command word. Desc: Configures options on AKO I2C bus master chip. SLRD (b0) - 0 if INT's for slave reads should occur for every byte, 1 if INT's should occur only as often as needed (largest burst size reached or stop/repeated start condition received). MARD (b1) - 0 if INT's for master reads should occur for every byte, 1 if INT's should occur only as often as needed (largest burst size reached or stop/repeated start condition received). SSINT (b2) - If 0, interrupts will only be generated for STARTs and STOPs which terminate a slave transfer by the bus master. If 1, interrupts are generated for all STARTs and STOPs which occur on the bus. SLACT (b3) - Set to 1 to enable bus master's slave capability, 0 to turn slave functionality off. BUSW (b4) - Set to 1 for the Start command to block until the bus becomes available to issue the START condition. When BUSW is 0, Start will immediatly fail when the I2C bus is being controlled by another master. b5 is currently undefined. It should set to 0 for compatibility with future versions of bus master. Name: Slave_Addr Command: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 1 | x | x | x | x | x | x | x | Data: Included in command word. Desc: The Slave_Addr command tells the bus master chip to which slave address it should respond. The lower 7 bits, b0-b6, indicate the upper 7 bits of the slave address (i.e. the slave address without the ~R/W bit). /*******************************/ /*** Status and data (reads) ***/ /*******************************/ The following data and status words may be read from the data bus by asserting ~CS (0) and asserting ~RD (0), then reading the 8 data lines. The data port only has valid data on it when the INT pin is asserted (high). Otherwise, reading the port produces an undefined result and may cause the AKOI2C to behave erratically. Name: Start_Stop Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 |STASTO| Type: Interrupt data. Data: Included in status word. Desc: This data is generated in response to an interrupt. If STASTO (b0) is 0, a START condition occurred on the bus. If STASTO is 1, a STOP condition occurred on the bus. The SSINT bit in the Configure control word affects the generation of this interrupt. Name: Addr_Match Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 0 | 0 | 0 | 1 | RD_WR| Type: Interrupt data. Data: Included in status word. Desc: This data is generated in response to an interrupt. The data is generated in response to an address match for the bus master's slave address. If RD_WR is 1, then the master is initiating slave read from the bus master. If RD_WR is 0, then the master is initiating a slave write to the bus master. If this indicates a slave read (RD_WR == 1), then the driver should immediatly write the byte to transmit to the bus master. Name: Xmit_Req Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Type: Interrupt data. Data: None. Desc: This data is generated in response to an interrupt. The interrupt and data are generated when the bus master is in slave transmitter mode and the master indicates that it would like more data. When this interrupt and data is received by the driver, it should immediatly write the byte to transmit to the bus master. Name: Data_Read Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 0 | 1 | MASL | S3 | S2 | S1 | S0 | Type: Interrupt data. Data: Included in status word, and (S3..S0) bytes following this data word. Desc: This data is generated in response to receiving data from the I2C bus. MASL (b4) is 1 if this data was read in master receiver mode. MASL is 0 if this data was read in slave receiver mode. The lower nibble, S0-S3 (b0-b3) indicate the number of data bytes which will follow this status word. The number of bytes following is ((status & 0x0f) + 1). Note that on a slave read, the first byte of the first data byte of the first Data_Read packet will be the slave address (slave address is transmitted back to the driver on slave receives). Name: Cmd_Success Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 0 | 1 | EC2 | EC1 | EC0 | CMD2 | CMD1 | CMD0 | Type: Interrupt data. Data: Included in status word. Desc: This data is generated in response to the completion of a command sent to the bus master. | CMD2 | CMD1 | CMD0 | meaning | +------+------+------+--------------------------------+ | 0 | 0 | 0 | Start command completed | | 0 | 0 | 1 | Stop command completed | | 0 | 1 | 0 | Master_Xmit command completed | | 0 | 1 | 1 | Master_Recv command completed | | 1 | 0 | 0 | Flush command comleted | | 1 | 0 | 1 | Reserved | | 1 | 1 | 0 | Reserved | | 1 | 1 | 1 | Reserved | Not all values of EC2..0 may be applicable for all commands. | EC2 | EC1 | EC0 | meaning | +------+------+------+--------------------------------+ | 0 | 0 | 0 | success | | 0 | 0 | 1 | arbitration lost | | 0 | 1 | 0 | not in control of bus | | 0 | 1 | 1 | slave did not ACK | | 1 | 0 | 0 | reserved | | 1 | 0 | 1 | reserved | | 1 | 1 | 0 | reserved | | 1 | 1 | 1 | reserved | Name: Status Format: | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | | 1 | CTRL | UTIL | BUSF | IDLE | u | BC1 | BC0 | Type: Status/interrupt data. Data: Included in status word. Desc: The status word is what is normally read from the bus master when no interrupts are pending. It may also be read on interrupts due to error conditions. BC1 (b1) and BC0 (b0) indicate the state of the internal FIFO command buffer. BC1 | BC0 | Buffer status -------+-------+------------------------ 0 | 0 | >= 40 bytes free 0 | 1 | 20 <= bytes free < 40 1 | 0 | 1 <= bytes free < 20 1 | 1 | buffer is full b2 is currently undefined. IDLE (b3) is 1 if the bus master is idle, 0 if it is executing commands. BUSF (b4) is 1 if the I2C bus is free (idle), 0 if the I2C bus is being controlled by a master. UTIL (b5) is 1 when the 16-bit I2C utilitization for the past 0.10 seconds is appended after this Status word. Indicates that the next two bytes read by the CPU will be the utilization count, MSB first. CTRL (b6) is 1 when the AKOI2C is currently in control of the bus. // end of document